Fix regression introduced in 47e9e8c
"security/tpm: replace CONFIG(TPMx) checks with runtime check":

Replace BIOS_WARN with BIOS_WARNING.

Change-Id: Id23cda2f5403effd2a4bda3852f0f300d0e62cdf
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81590
Reviewed-by: Elyes Haouas <[email protected]>
Tested-by: build bot (Jenkins) <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

Fixes error "Cache as RAM area is too full" during compilation of apu2.

Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

Starting from here CONFIG_TPM1 and CONFIG_TPM2 are no longer mutually
exclusive.

Change-Id: I44c5a1d825afe414c2f5c2c90f4cfe41ba9bef5f
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

- Remove unused CONSOLE region
- Shrink BOOTSPLASH to 512K
- Increase WP_RO by 512K

Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

Introduce a function to determine whether the number of cache sets is
a power of two. This aligns with common cache design practices that
favor power-of-two counts for efficient indexing and addressing.

BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified functionality on google/ovis and google/rex (including
a non-power-of-two Ovis configuration).

Change-Id: I819e0d1aeb4c1dbe1cdf3115b2e172588a6e8da5
Signed-off-by: Subrata Banik <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81268
Reviewed-by: Stefan Reinauer <[email protected]>
Tested-by: build bot (Jenkins) <[email protected]>

This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` configuration
at the SoC level for all MTL devices. This change streamlines the
configuration process, avoiding redundant selections on individual
mainboards.

BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot functionality on google/ovis and google/rex.

Change-Id: I3aa3a83c190d0a0e93c267222a9dca0ac7651f9c
Signed-off-by: Subrata Banik <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81271
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Stefan Reinauer <[email protected]>

Change-Id: I702013a6532534bf4fffa824bfd8e4a550abdd3a
Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: Ia3c6a35e5b37fb1a33cbf69c177b37298e04321e
Signed-off-by: Michał Żygowski <[email protected]>

Caching the RAMTOP causes issues with FSP MemoryInit for platforms
with DIMM modules. When memories are swapped, the training may
sometimes hang randomly. Seems to be a manifestation of the issue
described here: https://review.coreboot.org/c/coreboot/+/81269/
(despite the L3 cache sets is power of 2 on the tested i5-1235U SKU).

Disabling the RAMTOP caching make the memory training reliable no
matter how many times the DIMM modules are swapped/changed in slots.

RAMTOP was designed primarily for boot time optimizations in mind
(most likely for Chromebooks), so disable the RAMTOP caching for all
non-ChromeOS builds to boot reliably.

Signed-off-by: Michał Żygowski <[email protected]>

This is a workaround for modules that don't correctly populate the
serial number field in SPD.

When such modules are swapped, they generate the same CRC, causing FSP
to mistakenly consider them the same, and attempt to restore cached MRC
settings. This won't work when the modules are different.

As a workaround, force retrain the memory when RTC failure is detected.
Users are expected to reset their CMOS upon changing memory modules.

Change-Id: Iebb2810914b728317ce5ebd84b61667d2ba10529
Signed-off-by: Michał Kopeć <[email protected]>

Doesn't work with any FSP revs tested so far.

Change-Id: Ifd112230cdfc645e68f2146677008b200ae1b0a3
Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: Iae4bb0965aee8dad819320570b1852939a6ecab7
Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I4843ed215bff8a003799b399885950e69d1daf4d
Signed-off-by: Michał Kopeć <[email protected]>

Change-Id: I16517f3b76cf706650adafbe38af1d280b4d2f3d
Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

…le lines

Rationale: coreboot coding style guidelines
Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

Rename to page_ptr which more closely aligns with the SPD5 spec.

Signed-off-by: Michał Kopeć <[email protected]>

Reduce amount of nested if statements by adding separate branches for
DDR5, DDR4 and older SPD variants.

Signed-off-by: Michał Kopeć <[email protected]>

DDR5 SPD page length is 1024 bytes.

Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Kopeć <[email protected]>

This change fixes building NovaCustom V540TU, which previously errored
out due to missing MISCCFG_GPIO_PM_CONFIG_BITS definition.

Replace soc/gpio_defs.h with gpio.h which includes everything we need,
same as it was done for ADL in change 71266, and other SoCs.

TEST=Build and boot NovaCustom V540TU

Change-Id: I52a495f696258fc63752dd8e66e318e144bb768e
Signed-off-by: Michał Kopeć <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Sebastian Czapla <[email protected]>

updates:
- [github.com/pre-commit/pre-commit-hooks: v4.4.0 → v5.0.0](pre-commit/pre-commit-hooks@v4.4.0...v5.0.0)
- [github.com/talos-systems/conform: v0.1.0-alpha.27 → v0.1.0-alpha.30](siderolabs/conform@v0.1.0-alpha.27...v0.1.0-alpha.30)